1. Field of the Invention
The present invention relates to a method of treating a wiring substrate in a semi-additive process. Specifically, the present invention relates to a method of treating a wiring substrate, during manufacture of an IC package substrate, by pre-treating the wiring substrate with a pre-etching treatment liquid composition and then etching it with an etching liquid composition. The present invention also relates to a wiring substrate manufactured by the method above.
2. Description of Related Art
As an integration degree of IC (integrated circuit) is increased, a wiring rule of package substrate is now becoming increasingly finer. Along with this, a semi-additive process (hereinafter, may be referred to as the “SAP”) has been widely used for manufacture of the package substrate. The SAP process is performed as follows. First, a seed layer is formed on a substrate formed of an insulating layer by electroless copper plating. Subsequently, a resist pattern is formed on the seed layer by photolithography. On an exposed part of the seed layer formed of an electroless copper, a copper wiring pattern is formed by electrolytic copper plating. After the wiring pattern is formed, the resist is removed (a space formed by the removal of the resist pattern is to act as an inter-circuit space). The seed layer formed of the electroless copper positioned below the removed resist pattern is removed by etching. Thus, a wiring substrate is manufactured. Currently, the SAP realizes manufacture of the wiring substrate having a line/space (hereinafter, may be referred to as the “L/S”) as narrow as about 12 μm/13 μm. A finer wiring pattern is now demanded. However, it is difficult for a conventional etching process to fulfill the demand.
One disadvantage of the SAP is the following. When the electroless copper which forms the seed layer is etched away, the electrolytic copper which forms a wire is also etched away. Therefore, the wire formed of the electrolytic copper becomes thinner after the etching. For this reason, it is common that a pre-etching wiring pattern is formed in consideration of the amount which is to be etched away in a lateral direction thereof (hereinafter, the etching caused in the lateral direction of the wiring pattern will be referred to as a “side etching”). In a case where, for example, the amount of side etching caused when a wire having a post-etching L/S of 12 μm/13 μm is to be formed is 2 μm on one side, a pre-etching L/S of the wiring pattern is set to 16 μm/9 μm. In this manner, a wire having the post-etching L/S of 12 μm/13 μm can be formed. Now, it is assumed that the post-etching L/S is, for example, 6 μm/6 μm because of a requirement for a finer pattern. In this case, if the amount of side etching is 2 μm on each side as described above, the wiring pattern having the pre-etching L/S of 10 μm/2 μm needs to be set. When a width of space, namely, an area to be exposed to light is small, a light scattering is caused inside the resist and a light-exposed area of the resist is expanded. This makes it difficult to form the resist pattern. Even if the resist pattern is formed by adjusting a thickness of the resist or an exposure condition, a width of the resist pattern remaining after a development is small. This causes the resist, for example, to be delaminated or inclined during the development or washing. This makes it difficult to form the wires in a later step.
As described above, for forming an intended fine wiring pattern by the SAP, specifically for forming the resist pattern in accordance with a desired wiring rule, there is a limit on decreasing the width of a part of the resist that is to be exposed to light. Accordingly, it is strongly desired that in the step of etching the electroless copper which forms the seed layer, the amount of side etching of the electrolytic copper, which is to form the wires, is decreased significantly as compared with the amount caused by the conventional method.
As a method of suppressing the amount of side etching, it has been discussed to decrease a thickness of the seed layer so that the amount of etching of the seed layer and the wiring pattern is decreased. However, when the thickness of the seed layer is decreased, there occurs another problem that, for example, it is difficult to uniformize the thickness of the seed layer, and as a result, the wires themselves cannot be formed. Therefore, there is a limit on decreasing the thickness of the electroless copper plating which forms the seed layer. Currently, the thickness of the seed layer is 1 to 2 μm. In addition, a part of the seed layer that is to be the space needs to be removed completely. For this reason, the seed layer is commonly etched under a condition called “over-etching”, under which the etching time duration is made longer than is theoretically necessary to etch away a seed layer having a certain thickness or an etching liquid composition which realizes etching at a high rate is used.
It is now assumed that, for example, the thickness of the seed layer is 1 μm on average and the etching liquid composition and etching conditions by which the seed layer is etched away by 1 μm per minute are used. In this case, when over-etching of 100%, etching is performed for 2 minutes. Namely, when the thickness of the seed layer is 1 μm and the over-etching is 100%, the seed layer is actually etched away by 2 μm. Therefore, in the case where the electroless copper and the electrolytic copper are etched at the same rate, even if the thickness of the seed layer formed of the electroless copper is decreased, there is a limit on suppressing the amount of side etching.
Under such circumstances, an etching liquid having a high ratio of an etching rate of the electroless copper (ERN) to an etching rate of the electrolytic copper (ERE) (hereinafter, referred to as the “selection ratio ERN/ERE”) has been conventionally demanded. For example, Japanese Laid-Open Patent Publication No. (hereinafter referred to as JP-A-) 2009-221596 proposes an etching liquid containing a cupric ion source as a main component. JP-A-H6-330358 proposes an aqueous solution of ammonium persulfate.
JP-A-2009-120870 proposes an aqueous solution containing hydrogen peroxide-sulfuric acid as a main component. When copper is dissolved in this solution, reduction of hydrogen peroxide (a cathode reaction) occurs as well as the dissolution of copper (an anode reaction) as represented by expressions (1) and (2).Anode reaction: Cu→Cu2+2e−  (1)Cathode reaction: H2O2+2H++2e−→2H2O  (2)
JP-A-2009-120870 discloses that the etching rate can be controlled by promoting the anode reaction and the cathode reaction, in other words, by changing a concentration of an acid that dissolves copper ions or a concentration of hydrogen peroxide that supplies electrons.
JP-A-2006-9122 includes an example in which an azole such as a tetrazole, a triazole or the like is added to the etching liquid in order to adjust the etching rate of copper to a preferable level. JP-A-2006-9122 describes that since the azole is adsorbed to a surface of copper, which is an anode, the anode reaction represented by the above expression (1) is suppressed, and as a result, the etching rate is decreased.